1. Field of the Invention
The present invention relates to a semiconductor memory and a method of manufacturing the same and, more particularly, to a semiconductor memory comprising storage cells each of a combination of a MIS transistor and a capacitor and a method of manufacturing the same.
2. Description of the Prior Art
The dynamic RAM comprising storage cells each of a combination of a data storage capacitor and an access transistor has the highest possibility of being constructed in a high degree of integration among semiconductor memories and is employed in various electronic apparatus. Energetic activities for the technological development of dynamic RAMs have been extensively conducted. Some results of the technological development of dynamic RAMs are disclosed, for example, in J.P. Pub. Nos. 60-1952 and 60-19597.
As is described in "Trend of 4M and 16M DRAMs; Multilayer Capacitor and Trench Capacitor", Monthly Semiconductor World, pp.31-36, February 1988, dynamic RAMs are classified roughly into those of a multilayer capacitor type employing multilayer capacitors formed on a semiconductor substrate and those of a trench capacitor type employing trench capacitors formed on a semiconductor substrate. Most noticeable at the present as a RAM having the highest possibility of high-density integration is a static RAM of a trench capacitor type comprising trench capacitors formed in trenches formed in a semiconductor substrate, and access transistors formed directly above the trench capacitors. The construction of such a static RAM is illustrated in a sectional view in page 36 of the foregoing monthly magazine.
Efforts have been made to develop a method of fabricating a VLSI (very large scale integrated circuit) incorporating the foregoing semiconductor memories by using a so-called SOI (silicon-on-insulator) substrate formed by forming a thin single crystal silicon film over an insulative body. A SOI substrate is considered to be most excellent in crystallinity and characteristics among various SOI substrates.
In fabricating a SOI substrate through a process shown in FIGS. 16A, 16B and 16C, it is essential to lap a silicon wafer 101 selectively after applying a silicon wafer 105 to the silicon wafer 101 to finish the surfaces of insular silicon layers 106 formed in recesses formed by a SiO.sub.2 film flat and flush with the surface 103a of the SiO.sub.2 film 103 surrounding the insular silicon layers 106 without damaging. Various lapping methods have been proposed for such a purpose.
FIG. 17 shows a lapping apparatus for selective lapping. A laminated wafer 108 formed by laminating the silicon wafers 101 and 105 as shown in FIG. 16B is attached to a wafer holder 109, for example, with a wax. An abrasive disk 112 is formed by applying an abrasive pad 111 to the surface of a lapping disk 110. The abrasive disk 112 is rotated and a lapping liquid 114 is supplied to the surface of the abrasive pad 111 with the surface of the laminated wafer 108 to be lapped in contact with the abrasive pad 111 to lap the wafer 108. The lapping liquid 114 is an alkaline solution or an alkaline solution containing abrasive grains, which reacts on silicon and does not react on SiO.sub.2. The abrasive pad 111 is a very hard disk 116 as shown in FIG. 18, such as a ceramic disk or a carbide disk, a suede-finished soft urethane form cloth 117 as shown in FIG. 19.
J.P. Provisional Pub. (Kokai) No. 62-259769 discloses a lapping method of finishing the surface of a silicon wafer in a high flatness, which employs a polyurethane abrasive cloth and an amine solution as a lapping liquid for lapping. This known lapping method, however, refers to nothing about selective lapping for finishing a surface including both an insulative material and silicon in a flat surface by lapping.
Incidentally, in the static RAM of a trench capacitor type comprising storage cells each consisting of a trench capacitor and an access transistor formed directly above the trench capacitor, the n-type source-drain region (a region on the side of the capacitor) of a MIS access transistor is formed in a p.sup.- layer formed on a p.sup.+ -type semiconductor substrate by epitaxial growth. Therefore, it is possible that a depletion layer extending from the n-type region into the p-type epitaxial layer of a storage cell encounters with a depletion layer extending from the n-type source-drain region (a region on the side of the capacitor) of the adjacent storage cell when the storage cell are formed in a high density. Accordingly, this static RAM has an electrical disadvantage that current leakage increases even though the static RAM can be formed in a minute construction, and hence it is impossible to arrange the storage cells in a sufficiently high density.
Furthermore, since most conventional semiconductor memories are of a bulk silicon MOS type, it is difficult to reduce the parasitic capacitance across the bit line and the substrate. Accordingly, the open-bit construction, though excellent in integrating capability, is inferior in noise resistance and hence the open-bit construction is subject to limitation in the degree of integration. The semiconductor memory of a trench capacitor type is inevitably susceptible to soft errors and has a disadvantage that an optional bias voltage, for example, 0.5V.sub.cc, cannot be applied to the plate.